How to clear the screen on a 128x32 COG LCD display?

By admin 2026-08-06

How to Clear the Screen on a 128x32 COG LCD Display

To clear the screen on a 128x32 COG LCD display, you need to write zeros to every pixel in the display's internal RAM. This is typically done by sending a series of commands and data bytes over SPI or I2C, depending on your interface. For a common controller like the ST7565R or SSD1305, you set the column and page addresses, then send 128 * 32 / 8 = 512 bytes of zero data. For a 1-bit per pixel monochrome display, each byte controls 8 vertical pixels, so clearing the entire 128x32 grid requires exactly 512 bytes. If you're using a library like Adafruit_GFX, the display.clearDisplay() function does this automatically, but under the hood it's just writing zeros to the frame buffer. On a raw hardware level, you'd send command 0x21 (set column address) with start and end columns, then command 0x22 (set page address) with pages 0 to 3 (since 32 pixels / 8 bits per page = 4 pages), then blast 512 bytes of 0x00. Some controllers like the SH1106 use a different memory layout with 132 columns, but for a true 128x32 COG, the standard is 128 columns by 4 pages. The entire process takes about 5-10 milliseconds at a typical 4 MHz SPI clock, but if you're using a slower microcontroller or software bit-banging, it could take up to 50 ms. Always check the datasheet for your specific controller—some require a display enable command (0xAF) before the RAM write will take effect, and others need a contrast setting (0x81) to actually see the cleared state. If you're using a 128x32 cog lcd display with a built-in controller like the ST7565R, the clearing sequence is identical across most SPI-based modules.

The physical layer of clearing involves understanding the COG (Chip-on-Glass) construction. COG LCDs mount the driver IC directly on the glass substrate, which reduces pin count and improves reliability. For a 128x32 display, the driver IC typically has 128 segment outputs for columns and 32 common outputs for rows. The RAM is organized as a 128x32 matrix, but the addressing scheme depends on the controller. For example, the ST7565R uses a page-based system where each page is 8 rows tall. So page 0 covers rows 0-7, page 1 covers rows 8-15, page 2 covers rows 16-23, and page 3 covers rows 24-31. When you clear the display, you must write to all 4 pages. Each page has 128 columns, so 4 pages * 128 columns = 512 bytes total. Some controllers like the SSD1305 support vertical addressing mode, which lets you write sequentially without resetting the column address, but the byte count remains the same. If you're using a 3.3V logic level, the SPI signals (SCLK, MOSI, CS, DC) must be within 0.3V of VCC to avoid data corruption. Many COG modules include a built-in charge pump for the LCD drive voltage, which typically ranges from 8V to 12V. Clearing the screen doesn't affect the charge pump, but if you're seeing ghosting or incomplete clearing, check the contrast register (0x81) and the voltage regulator (0x2F). The default contrast value is often 0x3F, but you might need to adjust it to 0x20 for a 3.3V supply to get a clean black-on-white cleared state.

From a firmware perspective, the most common mistake is forgetting to set the display start line register. The ST7565R has a start line register (0x40-0x7F) that defines which row of RAM maps to the top of the display. If you clear the RAM but the start line is set to 32, the display will show a blank screen but shifted, making it look like the clear failed. Always set the start line to 0 (command 0x40) after power-on. Another critical detail is the segment remap register (0xA0 or 0xA1). If your display is mirrored left-to-right, you might need to set segment remap to 0xA1 to reverse the column order. Clearing the RAM still works, but the visual result will be flipped. For a proper clear, you should also disable the display inversion (command 0xA6 for normal, 0xA7 for inverted). If you're using a library that doesn't explicitly set these registers, the display might start in an unknown state. I've seen cases where a 128x32 COG LCD shows random pixels after clearing because the display was in power-save mode (command 0xAC) and the RAM write was ignored. Always wake the display with command 0xAF before clearing. The timing for the clear operation is also important: after sending the last byte of zero data, you need to wait at least 1 microsecond for the controller to process the data before sending the next command. Some controllers like the SSD1306 have a built-in "read-modify-write" cycle that can corrupt the RAM if you write too fast. A safe approach is to insert a 10-microsecond delay between each page write.

Let's look at the electrical characteristics that affect clearing. The COG LCD's pixel capacitance is about 10-20 pF per pixel, and the driver IC uses a charge-sharing technique to update the pixels. When you clear the screen, the driver must discharge all 4096 pixels (128 * 32 = 4096) to the common voltage level. This takes about 2-5 milliseconds depending on the internal oscillator frequency. The ST7565R has an internal oscillator that runs at 2.5 MHz typical, but it can be adjusted via command 0x24. A faster oscillator speeds up the RAM write but might cause flicker if the frame rate exceeds 100 Hz. For a 128x32 display, the typical frame rate is 60-80 Hz, and clearing the screen at 60 Hz means the entire RAM is rewritten every 16.7 milliseconds. If you're doing partial updates, you need to clear only the affected pages to avoid tearing. For example, if you're updating only the top 8 rows (page 0), you can clear just that page by writing 128 bytes of zero to page 0, leaving the rest of the RAM intact. This is useful for scrolling text or animations. The data sheet for the ST7565R specifies a minimum write cycle time of 400 nanoseconds for SPI, but most microcontrollers can't achieve that without a dedicated SPI peripheral. At 4 MHz, each byte takes 2 microseconds, so 512 bytes takes about 1 millisecond. Add in the command overhead (about 10 bytes), and the total clear time is around 1.1 milliseconds. In practice, with a 16 MHz Arduino, the clear function takes about 2.5 milliseconds due to library overhead.

Now, let's discuss the software implementation details. Here's a typical C function for clearing a 128x32 COG LCD using the ST7565R controller:

void clearDisplay() { // Set column address range (0 to 127) sendCommand(0x21); sendCommand(0x00); // Start column sendCommand(0x7F); // End column // Set page address range (0 to 3) sendCommand(0x22); sendCommand(0x00); // Start page sendCommand(0x03); // End page // Write 512 bytes of zeros for (int i = 0; i < 512; i++) { sendData(0x00); } }

This function assumes the display is already initialized with the correct bias, contrast, and display mode. If you're using a 128x32 COG display with an SSD1305 controller, the commands are slightly different: use 0x21 for column address and 0x22 for page address, but the SSD1305 also supports a "continuous horizontal scroll" mode that can interfere with clearing. Always disable scrolling (command 0x2E) before clearing. Another nuance is the "display start line" register: on the SSD1305, it's set via command 0x40-0x7F, but the default is 0, so you usually don't need to change it. However, some COG modules have a different pinout for the segment and common drivers, which can cause the display to appear shifted. For example, if the module uses a 90-degree rotated layout, the columns might be mapped to the rows in hardware. In that case, clearing the RAM still works, but the visual result is a blank screen rotated 90 degrees. To fix this, you'd need to remap the RAM in software, which is outside the scope of a simple clear.

Let's get into the data sheet specifics for a popular controller. The ST7565R datasheet from Sitronix specifies that the display RAM is 128x64 bits, but for a 128x32 module, only half the rows are connected. The unused rows (32-63) are still present in the RAM, and they can cause ghosting if not cleared. Some modules tie the unused rows to VSS or VDD, but others leave them floating. If you clear only the visible 4 pages, the unused rows might retain random data, which can leak into the visible area through capacitive coupling. To avoid this, clear all 8 pages (0 to 7) by writing 1024 bytes of zeros. This is a common trick used by experienced embedded engineers. The SSD1306 controller, on the other hand, has a 128x64 RAM but only 32 rows are physically connected on a 128x32 module. The datasheet recommends setting the multiplex ratio to 32 (command 0xA8, then 0x1F) to avoid addressing the unused rows. If you set the multiplex ratio to 64, the display will show a blank screen because the driver tries to address rows that don't exist. Always check the module's datasheet for the correct multiplex ratio. For a 128x32 COG, it's usually 32 or 39 (depending on the glass layout).

Now, let's talk about power consumption. Clearing the screen actually draws more current than displaying a static image because the driver IC has to charge and discharge all the pixel capacitors. For a typical 128x32 COG LCD, the current draw during a clear operation is about 2-5 mA at 3.3V, compared to 1-2 mA for a static image. If you're using a battery-powered device, you might want to minimize the number of clear operations. Instead of clearing the entire screen, you can overwrite the old data with new data, which avoids the extra current spike. The charge pump efficiency is around 70-80%, so the total power consumption for a clear is about 10-15 mW for 2 milliseconds. Over a day, if you clear the screen every second, that's about 0.5 mAh of battery drain. For a 200 mAh coin cell, that's negligible. But if you're clearing at 60 Hz (like in a video), the current draw can jump to 10 mA, which is significant. Some controllers have a "partial display" mode that lets you clear only a portion of the screen, reducing power. For example, the SSD1305 supports a "partial display on" command (0xA5) that blanks the entire display without clearing the RAM, saving power. This is useful for power-down scenarios.

Let's examine the physical layer of the COG module itself. The glass substrate has a thickness of 0.5-0.7 mm, and the driver IC is bonded using anisotropic conductive film (ACF). The pixel pitch for a 128x32 display is typically 0.4-0.5 mm, giving a total active area of about 51.2 mm x 12.8 mm. The clearance operation involves writing to the RAM, which is stored in the driver IC's SRAM. The SRAM is volatile, so the display will lose its content when power is removed. Some COG modules include a backup capacitor to maintain the RAM during a brief power loss, but this is rare. The SPI interface uses 4 pins: CS, DC, SCLK, and MOSI. Some modules also have a RESET pin, which should be held high during normal operation. If you pull RESET low, the display will be cleared automatically, but this is a hardware reset, not a software clear. The hardware reset clears all registers to default values, including the contrast and display mode, so you'll need to reinitialize the display after a reset. For a software clear, you don't need to touch the RESET pin. The DC pin (Data/Command) must be set low for commands and high for data. A common mistake is to leave DC high during the entire clear sequence, which sends the column and page addresses as data instead of commands, leading to a corrupted display. Always toggle DC correctly.

From a testing perspective, here's how to verify a successful clear. After sending the 512 bytes of zeros, read back the RAM if your controller supports it. The ST7565R does not have a readback feature, but the SSD1305 does. You can send a read command (0xE0) and clock out the data to verify that all bytes are zero. If you don't have readback, use a logic analyzer to check the SPI bus. The clear sequence should show 512 consecutive bytes of 0x00 on the MOSI line, with CS low and DC high. If you see any non-zero bytes, your code has a bug. Another method is to write a known pattern, clear, then write the pattern again and verify it's gone. For example, write 0xFF to all pixels (all black), clear, then write 0xAA (alternating pixels). If you see the 0xFF ghost, the clear didn't work. This is a common test in production lines for COG LCD modules. The ghosting can be caused by insufficient wait time between writes or incorrect page addressing. Some controllers have a "nop" command (0xE3) that you can use to insert a delay without affecting the RAM. Send a nop after each page write to ensure the controller has processed the data.

Let's compare the clearing process across different controllers that are commonly used in 128x32 COG displays. The table below shows the key differences:

Controller Comparison for 128x32 COG LCD Clear

| Controller | RAM Size | Pages Required | Clear Command Sequence | Special Notes |
|------------|----------|----------------|------------------------|---------------|
| ST7565R | 128x64 | 4 (0-3) | 0x21, 0x00, 0x7F, 0x22, 0x00, 0x03, then 512 bytes | Must set start line to 0x40 |
| SSD1305 | 128x64 | 4 (0-3) | 0x21, 0x00, 0x7F, 0x22, 0x00, 0x03, then 512 bytes | Disable scroll first (0x2E) |
| SSD1306 | 128x64 | 4 (0-3) | 0x21, 0x00, 0x7F, 0x22, 0x00, 0x03, then 512 bytes | Set multiplex to 32 (0xA8, 0x1F) |
| SH1106 | 132x64 | 4 (0-3) | 0x21, 0x00, 0x83, 0x22, 0x00, 0x03, then 528 bytes | Has 132 columns, pads with zeros |
| UC1701 | 128x64 | 4 (0-3) | 0x21, 0x00, 0x7F, 0x22, 0x00, 0x03, then 512 bytes | Needs bias set to 1/32 (0xA2) |

Notice that the SH1106 requires 528 bytes because it has 132 columns, even though only 128 are visible. The extra 4 columns are used for the segment driver's internal mapping. If you send only 512 bytes, the last 4 columns will retain old data, causing a vertical stripe on the right edge. This is a common pitfall when using SH1106-based 128x32 modules. Always check the datasheet for the exact column count. The UC1701 is similar to the ST7565R but requires a different bias setting. The bias setting determines the LCD drive voltage ratio, and if it's wrong, the cleared screen might show a faint background. For a 128x32 display, the bias is usually set to 1/32 (command 0xA2 for 1/32 bias, 0xA3 for 1/64). If you set it to 1/64, the contrast will be too low and the cleared pixels will appear gray instead of white. This is a subtle issue that can be mistaken for a failed clear.

Now, let's talk about the practical aspects of using a 128x32 COG in a product. If you're designing a battery-powered device, you might want to use the "sleep" mode to save power. The sleep mode (command 0xAE) turns off the display driver but retains the RAM. When you wake the display (0xAF), the RAM is still intact, so you don't need to clear it again. However, if you've been in sleep mode for a long time, the charge pump might have discharged, and the display might show a brief flash of random pixels when waking. To avoid this, clear the screen after waking. The wake-up time from sleep is about 10-100 microseconds, depending on the controller. The clear operation after wake-up should be delayed by at least 1 millisecond to allow the charge pump to stabilize. Some controllers have a "display on" command that automatically clears the screen, but this is not standard. The ST7565R, for example, does not clear the RAM on power-on, so you must clear it